*PADS-POWERLOGIC-V5.2* DESIGN EXPORT FILE FROM PADS LOGIC V2004.1
*SHT*   1 $$$NONE -1 $$$NONE
*PARTTYPE*   ITEMS

$GND_SYMS UND  2   2   2     0   0
G:DGND 0 1
1.0.G
G:PWRGND 0 1
2.0.G
SIGPIN 1.50.DGND
SIGPIN 2.50.PWRGND

$PWR_SYMS UND  2   2   2     0   0
G:+5V 0 1
1.0.P
G:BUBBLE 0 1
2.0.P
SIGPIN 1.50.+5V
SIGPIN 2.50.+5V

PS2802-4-A SOP  4   0   0    16   0
G:PS2802 0 4
1.0.U.AN 2.0.U.CATH 15.0.U.EMIT
16.0.U.COL
G:PS2802 0 4
3.0.U.AN 4.0.U.CATH 13.0.U.EMIT
14.0.U.COL
G:PS2802 0 4
5.0.U.AN 6.0.U.CATH 11.0.U.EMIT
12.0.U.COL
G:PS2802 0 4
7.0.U.AN 8.0.U.CATH 9.0.U.EMIT
10.0.U.COL

RES0805 RES  1   0   0     0   0
G:RESZ-H:RESZ-V:RESB-H:RESB-V 0 2
1.1.U 2.1.U

MMSZ5260BT1 DIO  1   0   0     2   0
G:ZENER 0 2
1.0.U 2.0.U

43650-0400 CON  1   0   0     6   0
G:43650-0400 0 4
1.0.S 2.0.S 3.0.S
4.0.S

*END*     OF ASCII OUTPUT FILE
