*PADS-LOGIC-V9.0* DESIGN EXPORT FILE FROM PADS LOGIC VVX.2.15

*SCH*
UNITS 0
USERGRID 100 100
SHEET SIZE A
BORDER NAME Default_A
JOBNAME "Signal Test"
TEXTSIZE 60 0
LINEWIDTH 2

*SHT* 1 Sheet1 0 Root

*PART*
R1 RES_0805 1000 2000 0 0 50 69 50 69 1 0 0 0 0 0
"Arial"
"Arial"
1050 2100 0 0 50 69 0 "Arial"
Ref.Des.

R2 RES_0805 3000 2000 0 0 50 69 50 69 1 0 0 0 0 0
"Arial"
"Arial"
3050 2100 0 0 50 69 0 "Arial"
Ref.Des.

U1 IC_NAND 5000 2000 0 0 50 69 50 69 1 0 0 0 0 0
"Arial"
"Arial"
5050 2100 0 0 50 69 0 "Arial"
Ref.Des.

*CONNECTION*
*SIGNAL* VCC 0 0
R1.1 U1.14 2 0
1000 2000
2000 2000
U1.14 @@@D1 2 0
2000 2000
2000 3000
*SIGNAL* GND 0 0
R2.2 U1.7 2 0
3000 2000
4000 2000
*SIGNAL* NET1 0 0
R1.2 R2.1 2 0
1000 2000
1500 2000
R2.1 @@@D2 2 0
1500 2000
3000 2000
U1.1 @@@D2 2 0
3000 2000
4000 2000
U1.2 @@@D3 2 0
4000 2000
5000 2000
*SIGNAL* OUTPUT 0 0
U1.3 @@@O1 2 0
5500 2000
6000 2000

*END*
